Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6-T) SRAM, eight-transistor (8-T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into, or read a bit from, the SRAM cell.
With the down-scaling of integrated circuits, the power supply voltages of the integrated circuits are reduced, along with the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which are used to indicate how reliably the bits of the SRAM cells can be read from and written into, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations. Further, with the reduction in the power supply voltages, the speeds of the operations are also reduced.
Various approaches have been explored to reduce the supply voltage of SRAM cells in read and write operations. For example, FIG. 1 illustrates a portion of a column of self-feedback six-transistor (6-T) SRAM cells including SRAM cell 100 and SRAM cell 200. In each of the SRAM cells 100 and 200, pass-gate transistors 102/104 and 202/204 are dual-gate transistors including front gates 110/114 and 210/214 and back-gates 112/116 and 212/216. The back-gates 112/116 and 212/216 of the pass-gate transistors are connected to storage nodes 106/108 and 206/208, respectively. In a write operation, SRAM cell 100 is selected for writing a “1” (VDD) from bit-line BL and a “0” (VSS) from bit-line BLB. SRAM cell 200 is unselected. Node 106 is at a high voltage, and hence the back-gate 112 of pass-gate transistor 102 is turned on. Therefore, pass-gate transistor 102 is enhanced during the write operation, and the write ability of SRAM cell 100 is enhanced.
The above-discussed structure, however, suffers from drawbacks. For unselected SRAM cell 200, assuming node 206 also stores a “1,” the respective pass-gate transistor 202 is also enhanced due to the fact that the back-gate of pass-gate transistor 202 is connected to node 206. Therefore, pass-gate transistor 202 may be partially turned on, or at least has a high leakage current since bit-line BLB is at voltage VSS. This may cause an erroneous flip of SRAM cell 200. An additional problem of the convention structure is that SRAM cells 100 and 200 may need to be laid out in such a way that the P-well or N-well regions have zigzag patterns, which adversely affect the scalability of the respective SRAM cells. Alternative solutions are thus needed to solve the above-discussed problems.